1. Field of the Invention
The present invention generally relates to a method of minutely producing a highly integrated semiconductor device. More particularly, the present invention relates to a method of forming a contact hole for electrically connecting elements formed on a semiconductor substrate to one another or to other elements outside the semiconductor substrate.
2. Description of the Related Arts
Recently, due to the development of a VLSI into a higher speed type circuit reducing the wiring resistance of a semiconductor device has been demanded. Particularly in each element of the semiconductor device, reducing the contact resistance at a contact part which electrically and mutually connects a metal wiring member and a semiconductor substrate, has been demanded. The contact resistance referred to here comprises two resistances: the contact resistance between a wiring metal and an Si substrate, and the contact resistance of the metal wiring filling a contact hole.
As the size of the semiconductor device is decreased to achieve the higher integration of the VLSI, the size of the contact hole has become smaller, and the aspect ratio (the ratio of contact hole depth to contact hole size) has become larger. Along with this increasingly minute arrangement of the VLSI, the contact resistance has become larger due to decrease in contact area, and the step coverage or buried condition of the wiring metal in the vicinity of the contact hole has degraded due to the increase in the aspect ratio of the contact hole. In addition, there is a problem that if the step coverage is further degraded, the wiring metal will be disconnected within the contact hole.
As a measure to counter the increase in the contact resistance, it has generally been known that a metal with a high melting point, such as Ti, or the silicide thereof is used to reduce the contact resistance.
As a measure to counter the disconnection of the wiring metal within the contact hole, the techniques illustrated in FIGS. 4A to 4C and FIGS. 5A to 5C have generally been known. These techniques will now be described referring to these figures. It should be noted, however, that these figures illustrate those cases in which the contact is provided in the diffusion layer of an MOSFET.
As illustrated in FIG. 4A, an LOCOS film 11 is formed on an Si substrate 10, a gate insulating film 12 and a gate electrode 13 are formed thereon, a source/drain diffusion region 14 is formed, and an interlayer insulating film 15 is formed on top. Generally, the interlayer insulating film 15 uses a BPSG (boronphosphosilicate glass) film 15 containing boron and phosphorus, which is a CVD oxide film containing impurities, to insulate the wiring metal from the gate electrode and level the wafer surface. Furthermore, making use of the fluidity of the BPSG film at a high temperature, the first heat treatment (reflow treatment generally at 900.degree. C..+-.50.degree. C.) is performed to level the substrate. Then, as illustrated in FIG. 4B, a contact hole 17 is formed by anisotropic etching in photolithographic process using a photoresist 16 as a mask. Next, as illustrated in FIG. 4C, the second heat treatment is performed at the same temperature as that of the reflow treatment to round the square corners of the opening part 18 of the contact hole 17. By these two heat treatments, the surface is levelled and the opening part 18 is shaped into a funnel with an "upwards convex" curvature.
On the other hand, in the conventional method illustrated in FIGS. 5A to 5C, and as described above, the BPSG film 15 is formed and a reflow treatment is performed for levelling the BPSG film 15 as illustrated in FIG. 5A. Isotropic etching is applied to improve the shape of the opening part 18 of the contact hole as illustrated in FIG. 5B, and then anisotropic etching is applied down to the Si substrate to form the funnel shaped contact hole 17.
In the former method illustrated in FIGS. 4A to 4C; and, however, two heat treatments are performed to improve the shape of the contact hole formed in the interlayer insulating film after forming the source/drain region. Accordingly, this process poses a problem in that, against the demand that the junction depth of the source/drain region should be shallowed to meet the requirements of the minute production of the VLSI, the impurities are further diffused by the excessive heat treatments and consequently the junction depth of the source/drain region is deepened. Another problem is that, as the second heat treatment is performed after the contact hole is formed, impurities forming the source/drain layer separate from the Si substrate surface to the outside, or boron and phosphorus separated from the BPSG film at the side of the contact hole diffuse to the Si substrate surface, and therefore the impurity density in the source/drain surface changes and contact resistance is degraded.
In the latter method illustrated in FIGS. 5A to 5C, as the opening part of the contact hole formed in the interlayer insulating film is shaped with a "downwards convex" curvature, when the metal particles of the wiring metal film actively migrate in the formation of the wiring metal film, the viscosity between the BPSG film and the metal particles becomes lower, and consequently a ball shaped "pool" of the metal film is caused around the opening part of the contact hole. When this "pool" develops larger, it clogs the passage of the metal particles to the inside of the contact hole. As a result, a hollow part is formed within the contact hole. Consequently, the wiring resistance within the contact hole increases, or the wiring is disconnected and the production yield falls.